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Course Description
| Altera FLEX Application Workshop |
Date: from 19 Jun 2000 to 20 Jun 2000 2 day(s)
English Berkshire, UK
650,00 Euro 30%
Research by Altera has shown that engineers who have attended training in their technologies create designs that are 90% faster and 45% smaller, resulting in an average 70% parts cost saving!
This workshop is therefore a must for all engineers using Altera FLEX technologies in their designs. Based upon Altera`s own training materials, the workshop presents the details of all technology features found in the FLEX family of devices and how to use the MAX+PLUS II place and route software to obtain the most efficient results.
- Overview of FLEX families
- FLEX Architecture construction and features
- Efficient implementation of specific functions such as arithmetic functions, control logic, and RAM
- Accessing technology specific features such as clock buffers, global nets and power-on resets
- Understanding and using the interconnect efficiently
- Making good use of the IO cells available in the different FLEX technologies
- Understanding and managing device timing to achieve the fastest device speed
- How to use the In Circuit Reconfigurability features of FLEX devices
The main MAX+PLUS II software issues covered:
- How MAX+PLUS II fits into an overall system design flow
- How to use LPM and Megafunctions to make your design more efficient
- Controlling the place and route and floor planning tools to achieve the best results
- How to use the built in timing analysis tools
Engineers who will use Altera FLEX technology in real design projects
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