Course Description

Duration 4 day(s)

Language English    Venue Berkshire, UK

Country 

Course fee 1300,00    Currency UK£    Discount Academic

Description
This workshop focuses on teaching both the Verilog language and its application to real design projects through simulation
and synthesis. The workshop contains over 50% lab work and can be taken in two separate modules if required.

- Introduction to Verilog Based Design Workshop
- Advanced Application of Verilog Workshop

The main topics covered:
Basic and advanced language features commonly used on today`s designs
How to write Verilog for synthesis of ASICs and FPGAs
Design organisation and management issues
Creation of stimulus through Verilog test benches
How Verilog is best applied to real designs

Course Contents and Time Table
Day 1
Workshop Introduction.
Verilog Application Introduction.
Verilog Language Introduction.
Verilog Variables and Types.
Verilog Operators.
Concurrent and Sequential.

Day 2
Sequential Statements.
Verilog Coding Styles.
Synthesis Process.

Day 3
Definition of RTL code.
Synthesis Coding Styles.
Specifying Timing in Verilog.

Day 4
Tasks and Functions.
Introduction to Testbenches.
System Tasks and Functions.
Advanced Verilog Testbenches.

Audience
Engineers who need to use Verilog in real design projects

Further information
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