Course Description

Duration 5 day(s)

Language English    Venue Lausanne, Switzerland

Country 

Course fee 1900,00    Currency EURO    Discount 15% discount applies for students

Course Contents and Time Table
MONDAY, AUGUST 23

8:30-12:00 am
MOS and Bipolar: Modes of Operation and Models
Eric Vittoz, CSEM

1:30-5:00 pm
Passive Components and Parasitic Effects
Eric Vittoz, CSEM

TUESDAY, AUGUST 24

8:30-10:00 am
Layout Techniques for Analog Circuits
Eric Vittoz, CSEM

10:30-12:00 am& 1:30-3:00 pm
Elementary Building Blocks
Eric Vittoz, CSEM

3:30-5:00 pm
Voltage References
Eric Vittoz, CSEM

WEDNESDAY, AUGUST 25

8:30-12:00 am & 1:30-5:00 pm
Analog Functional Blocks
Willy Sansen,KU Leuven

THURSDAY, AUGUST 26

8:30-12:00 am
CMOS Off-Chip Drivers
Rinaldo Castello,University of Pavia

1:30-5:00 pm
Analog Circuit Design Techniques
Herman Casier,AMI Semiconductor

FRIDAY, AUGST 27

8:30-10:00 am
Technology Effects and Other Limitations for Mixed-Signal ASICs
Herman Casier,AMI Semiconductor

10:00-12:00 am & 1:30-5:00 pm
Switched-Capacitor Circuit Design
Gabor Temes, OSU

Audience
The prerequisite of the course is a basic knowledge of semiconductor devices and circuits. All levels of expertise (beginners, medium and advanced engineers) can benefit of this training. Also, company managers and marketing engineers may find useful information in the trends of modern techniques and applications presented in these classes.

Lecturers
- Eric Vittoz, CSEM
- Willy Sansen,KU Leuven
- Rinaldo Castello,University of Pavia
- Herman Casier,AMI Semiconductor
- Gabor Temes, OSU

Further information
Vlado Valence
EPFL-LEG
Buildign EL-B
1015 Lausanne
Tel: +41-21-695-2222
Fax: +41-21-695-2220
Technical email: valence@mea