Course Description

Duration 5 day(s)

Language English    Venue Lausanne, Switzerland

Country 

Course fee 1900,00    Currency EURO    Discount 15% discount applies for students

Course Contents and Time Table
MONDAY, AUGUST 23

8:30-10:00 am
Ultra Deep Submicron Design Challenges An Overview
Jan Rabaey,UC Berkeley

10:30-12:00 am
Issues in LP Design - Introduction & Basics
Jan Rabaey,UC Berkeley

1:30-3:00 pm
Issues in Low-Power Design - Circuit Level
Jan Rabaey,UC Berkeley

3:30-5:00 pm
Issues in Low-Power Design - Architecture and System Level
Jan Rabaey,UC Berkeley

TUESDAY, AUGUST 24

8:30-10:00 am
Advanced CMOS Design
Michael Smith,CTO, iReady

10:30-12:00 am
Advanced FPGA Design
Michael Smith,CTO, iReady

1:30-3:00 pm
Current State of the Art in ASIC Design
Michael Smith,CTO, iReady

3:30-5:00 pm
A Complete System Design Example
Michael Smith,CTO, iReady

WEDNESDAY, AUGUST 25

8:30-12:00 am
High Performance Digital Design
Pat Bosshart,Texas Instruments

1:30-3:00 pm
Interconnects
Martin Rau, Siemens

3:30-5:00 pm
Synchronization with PLL and DLL
Martin Rau, Siemens

THURSDAY, AUGUST 26

8:30-10:00 am
High Performance Interconnect Design
Sachin Sapatnekar,Uni. of Minnesota

10:30-12:00 am
High Performance Logic Design
Sachin Sapatnekar,Uni. of Minnesota

1:30-5:00 pm
Asynchronous Circuits and Architectures for System-on-Chip Integration
Christoph Heer,Infineon Technology

FRIDAY, AUGST 27

8:30-12:00 am
Very High-Speed IC Design Methods
Yusuf Leblebici,EPFL

1:30-5:00 pm
Low-Power Systems on Chips (SoCs)
Christian Piguet, CSEM

Audience
The prerequisite of the course is a basic knowledge of semiconductor devices and circuits. All levels of expertise (beginners, medium and advanced engineers) can benefit of this training. Also, company managers and marketing engineers may find useful information in the trends of modern techniques and applications presented in these classes.

Lecturers
- Jan Rabaey,UC Berkeley
- Michael Smith,CTO, iReady
- Pat Bosshart,Texas Instruments
- Martin Rau, Siemens
- Sachin Sapatnekar,Uni. of Minnesota
- Christoph Heer,Infineon Technology
- Yusuf Leblebici,EPFL
- Christian Piguet, CSEM

Further information
Vlado Valence
EPFL-LEG
Buildign EL-B
1015 Lausanne
Tel: +41-21-695-2222
Fax: +41-21-695-2220
Technical email: valence@mea