Course Description

Duration 5 day(s)

Language English    Venue Marlborough, Wiltshire, UK

Country 

Course fee 1625,00    Currency UK£    Discount 30% Europractice members

Description
Overview:
This five day VHDL workshop is designed for engineers who are new to using the VHDL language, and is unique in the way that it covers not just language issues, but also goes in depth into the issues surrounding the successful use of synthesis and verification on today`s typical real world design projects. Based on the in-depth experience of both our own staff and forty of the world`s foremost design consultants who teach for us, the course presents the latest methods available for the successful design of complex ASIC and FPGA devices using VHDL.

Course Contents and Time Table
VHDL Application Workshop Course Agenda

Days 1-2: Language Basics and Application Overview
• VHDL application overview
• VHDL language introduction
• Design units and main language concepts
• Signals and drivers
• Pre-defined and user defined types
• Array, enumerated and record types
• Standard logic
• Logical and relational operators, concatenation and array slices
• Processes and sequential statements
• Concurrent statements and equivalent processes
• Simulation execution, sensitivity lists and wait statements
• Variables and variable use
• Arithmetical operators, overloading and arithmetic packages
• Overview of coding styles for testbenches, RTL and behavioral code
• Datapath and control examples of behavioral and RTL modeling
• The synthesis process and methodology overview

Day 3: Synthesis Coding Styles in Depth
• RTL coding styles and guidelines for efficient synthesis
• Describing combinatorial logic
• Inferring registered logic
• Simulation, synthesis and optimization of arithmetic operators
• Coding styles for efficient hardware synthesis
• FSM`s and state vector encoding
• Synthesis of variables
• Modeling timing in VHDL
• Delay modeling, gate level simulation and VITAL

Day 4-5: Language Constructs, Coding Styles & Strategies for Verification
• Procedures and functions
• Overloading, type qualification and resolution functions
• Generics, generates and blocks
• Unconstrained, type indexed and multi-dimensional arrays
• Types, sub-types, closely-related types and type conversions
• Coding styles and strategies for generating test stimulus
• Creating clocks and resets
• Reading and writing data using file I/O
• Script driven testbenches
• Data and message outputs for efficient verification
• Result visualization
• Design organization and management
• Options and strategies for using configurations
• Compilation, elaboration, initialization and simulation
• Efficient use of packages

Workshop Labs
The labs have been designed to follow on from each other over the course of the workshop, building on code developed in each lab to create an overall design project.

The first few labs get you familiar with the tools you are using and the basic steps involved in simulating and synthesizing a small design. Subsequent labs are based upon design modeling and verification issues that are typically encountered in a real world design project.

The lab sessions include:-
• Familiarization with simulation and synthesis tools
• Describing and verifying combinatorial logic
• Creating registered logic
• Using vector arithmetic packages
• Structural design and hierarchy
• Verification using visualization of results
• State machine design
• Verification using script driven, self-checking testbenches
• Integration and verification of a third-party IP model

Audience
Prerequisites
Students should be familiar with the issues and principles of digital hardware design, and how to operate the user interface and a text editor within a PC or workstation based operating system.
While some previous exposure to at least one other software language would be useful, it is not essential.

Lecturers
Trainer Expertise
Esperan has over 40 regular trainers, who are themselves design consultants working on some of the world`s most advanced projects ranging from multi-million gate ASIC projects to those involving state of the art programmable logic devices.
We have hand-picked each trainer for their up to date experience, combined with their presentation skills and flair for helping others to learn. You will find your trainer takes a very personal approach, helping each individual to make the very most of their time in the classroom.

Further information
Gill Loader or Julia Brazier at Esperan on telephone number
+44 1672 520101 or email us at info@esperan.com