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Course Description
 | Essential VHDL and Synthesis for Altera FLEX Technology |
Date: from 21 Sep 2000 to 22 Sep 2000
2 day(s)
English Ramsbury, Wiltshire UK
650,00 UK£ 30% for Europractice
Overview:
Understanding VHDL for synthesis and a specific programmable logic technology is one thing. Learning how to write code and use specific synthesis and implementation tools to achieve the most efficient design is quite another.
This workshop is designed to fill that gap. These hands-on exercises take engineers through the implementation of the most common and troublesome types of design problems, such as design flow problems, integration of RAM, ROM, arithmetic functions, state machines and bi-directional asynchronous to name but a few. These features are all integrated into a single, complete design application (the "Edge Filter") which Esperan have specifically created to show the efficient use of VHDL on a real project. Once attendees have gone through the complete design flow using the most generic VHDL coding style, they then work on advanced coding styles and software options to obtain the optimal implementation.
Since different synthesis tools have different capabilities, the workshop will teach how to obtain the best results with your choice of synthesis tool from either Exemplar, Synplicity or Synopsys.
Detailed Agenda
Day 1
Altera Workshop Introduction: course objectives, conventions used, overview of agenda.
Altera Technology Overview: an overview of the Altera FLEX architecture and features.
Topics covered include:- FLEX 10K devices, architectural block diagram, logic element, cascade chain, carry chain, Embedded Array Block (EAB), EAB architecture, I/O element, summary.
Definition of RTL Code (RTE): a reminder of the RTL coding style, and some of the main issues in writing code which is portable between different synthesis tools.
Topics covered include:- concepts of the combinational and clocked process, the need for complete sensitivity lists in a combinational process, avoiding the synthesis of transparent latches from incomplete assignments, summary of the rules for synthesis of combinational logic, a detailed look at the different ways of describing a rising clock for synthesis and recommendations for making code portable, inferring asynchronous reset registers, summary of the rules for a clocked process, summary.
Altera Design Flow Description: a detailed look at the design flow for the simulation, synthesis and implementation of an Altera design.
Topics covered include:- design flow overview, tool interfaces, synthesis constraints, synthesis of operators, module generation, generating memory models, place and route, timing analysis, cliquing, gate level simulation, design flow issues, summary.
Language Specific Optimizations: an in-depth look at VHDL coding techniques for effective targeting of programmable logic architectures.
Topics covered include:- IF versus CASE statement synthesis, IF-ELSIF versus IF-ENDIF structures, Infering latches and registers, state machine overview, state machine structures, state vector encoding, safe state machines, resource sharing, summary.
Edge Filter Design: an overview of the lab sessions and an introduction to the Edge Filter design upon which the labs are based.
Topics covered include:- Edge Filter functionality, design partitioning and hierarchy, summary of design features, overview of day 1 labs, overview of day 2 labs.
Lab Exercises: The lab exercises on day 1 are designed to familarize students with taking the 8,000 gate Edge Filter design through the complete design flow using their chosen set of simulation and synthesis tools. The flow includes HDL based simulation using a sophisticated testbench, synthesis, implementation,
and back annotated gate level simulation within the testbench environment using post layout timing information.
Day 2
Altera Technology Specific Optimizations: detailed look at the optimisation techniques for targeting Altera technology and architecture including the pros and
cons of using technology specific cells
Topics covered include:- Issues affecting quality of results, implementing latches and registers, resets and power-up initialisation, global low skew nets, Library of Parameterised Macros (LPM`s), Altera Mega Wizard, implementing RAM`s and ROM`s, Phase Locked Loops, instantiation options, ROM based state machines, EAB state machine restrictions, efficient counters, carry chains, cascade chains, I/O modules, summary.
Lab Exercises: The lab exercises on day 2 take most of the day, and involve optimizing the implementation of each block of the Edge Filter design to achieve the smallest and fastest implementations. Techniques used to achieve this are a mixture of changing HDL coding styles, and using features of the synthesis and Altera implementation software.
The workshop is designed for:
- Engineers who will be using VHDL to target an Altera FLEX device
Prerequisites:
- Previous VHDL for synthesis experience or recent attendance at a VHDL course such as Esperan`s five day "VHDL Application Workshop".
- Previous knowledge of Altera FLEX technology and MAX+PLUS II implementation software.
Esperan
Unit 1 Hilldrop Lane
Ramsbury
Wiltshire
SN8 2RB
UK
Tel +44(0)1672 520101
Fax +44(0)1672 521039
Email info@esperan.com
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