Course Description

Duration 4 day(s)

Language English    Venue England, UK

Country 

Course fee 1600,00    Currency UK£    Discount 30% Europractice member

Description
Overview:

Understanding VHDL for synthesis and a specific programmable logic technology is one thing; learning how to write code and to use specific synthesis and place& route tools to achieve the most efficient design is quite another.

This workshop is designed to fill that gap. The hands-on exercise takes engineers through the implementation of the most common and troublesome types of design problems, such as RAM, arithmetic functions, state machines and bi-directional asynchronous IO to name but a few. These features are all integrated into a single, complete design application which we have specifically created to show the efficient use of VHDL on a real project. Once attendees have gone through the complete design flow using the most generic VHDL coding style, they then work on advanced coding styles and software options to make the most optimal implementation.

Since different synthesis tools have different capabilities, the workshop will teach how to obtain the best results with your choice of FPGA synthesis tool from either Exemplar, Synplicity or Synopsys.

Course Contents and Time Table
Introduction to Xilinx Products
Virtex Architecture
The Select I/O and its Applications
Delay Locked Loop (DLL) Usage and Applications
RAM Resources and Applications
Routing Resources
Reduction in routing congestion
IO interconnect and internal buses


Xilinx Tool Flow
Overview of the Xilinx Tool Flow
Implementation and the Flow Engine
Interpreting Reports
Global Timing Constraints
Introduction to the Timing Analyzer
LogiBLOX and the Core Generator
Implementation Options
Re-entrant Routing and Multi-Pass Place and Route
Viewing Your Design with the Floorplanner
The FPGA Configuration Process

Virtex Architecture Review
Configurable Logic Block (CLB) and Programmable Routing Matrix
Select I/O and Delay Locked Loops (DLL`s)
SelectRAM
Xilinx Virtex Design Flow
Module Generation
Synthesis with Constraints
Place and Route
Timing Analysis and Gate Level Simulation
Language Specific Optimizations
Conditional Construct Synthesis
State Machines Styles
Resource Sharing and Pipelining
Lab Overview and Introduction to Lab Design


Virtex Technology Specific Issues
Implementing Latches and Registers
Using the Clock Enable Pin
Module and Memory Generation Options
Efficient Use of the Architecture

Lab Exercises:

The lab exercises are designed to familarize students with taking the 8,000 gate Edge Filter design through the complete design flow using their
chosen set of simulation and synthesis tools.
Iinvolve optimizing the implementation of each block of the Edge Filter design to achieve the smallest and fastest implementations. Techniques used to achieve this are a mixture of changing HDL coding styles, and using features of the synthesis and Xilinx
implementation software.

Audience
The workshop is designed for:

- Engineers who will be using VHDL to target a Xilinx Virtex technology device

Prerequisites:

- Previous VHDL for synthesis experience or recent attendance at a VHDL course such as Esperan`s five day "VHDL Application Workshop".
- Previous knowledge of Xilinx Virtex technology and Implementation software either from a design project or from attending a training course.

Further information
Gil Loader
Esperan
Tel +44 1672 520101
Fax +44 1672 521039
Email info@esperan.com

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