Course Description

Duration 5 day(s)

Language English    Venue The Ivy House Hotel, Marlborough,UK

Country 

Course fee 1625,00    Currency UK£    Discount 30% for Europractice Members

Description
Overview
This five day Verilog workshop is designed for engineers who are new to using the Verilog language, and is unique in the way that it covers not just language issues, but also goes in depth into the issues surrounding the successful use of synthesis and verification on today`s typical real world design projects. Based on the in-depth experience of both our own staff and forty of the world`s foremost design consultants who teach for us, the course presents the latest methods available for the successful design of complex ASIC and FPGA devices using Verilog.

Course Contents and Time Table
Verilog Application Workshop Course Agenda

Days 1-2: Language Basics and Application Overview
• Verilog application overview
• Verilog language introduction
• Design objects and main language concepts
• Lexical conventions
• Data types and logic system
• Net, register and parameter data types
• Choosing the correct data type
• Memory arrays and addressing
• Structural modeling
• Module and primitive instantiation
• Logic strength modeling
• Operator concepts and examples
• Procedures and timing control
• Blocking and non-blocking procedural assignments
• Conditional and loop statements
• Continuous assignments
• The synthesis process and methodology overview

Day 3: Synthesis Coding Styles in Depth
• High level Constructs
• Tasks and functions
• Explicit Finite State Machines
• Synthesis modeling style
• Combinatorial and synchronous procedural blocks
• Continuous assignments
• Conditional statements
• Blocking and non-blocking assignments for synthesis
• Modeling resets
• Simulation, synthesis and optimization of mathematical operators
• Coding styles for efficient hardware synthesis
• State machine descriptions
• If and case statement structures

Days 4-5: Language Constructs, Coding Styles & Strategies for Verification
• Tasks and functions
• Single and multiple module task calls
• Disabling tasks and named blocks
• Support for verification
• System tasks and functions
• File input and output
• Coding styles and strategies for generating test stimulus
• Design and testbench organisation
• In-line, looped and arrayed stimulus
• Vector capture and playback
• Creating clocks
• Script driven testbenches
• Data and message outputs for efficient verification
• Modeling timing
• Delay modeling, timing checks and timing flow
• Memory Modeling
• RAM`s, ROM`s and bi-directional ports
• User defined primitives

Audience
Prerequisites
Students should be familiar with the issues and principles of digital hardware design, and how to operate the user interface and a text editor within a PC or workstation based operating system. While some previous exposure to at least one other software language would be useful, it is not essential.

Lecturers
Trainer Expertise
Esperan has over 40 regular trainers, who are themselves design consultants working on some of the world`s most advanced projects ranging from multi-million gate ASIC projects to those involving state of the art programmable logic devices. We have hand-picked each trainer for their up to date experience, combined with their presentation skills and flair for helping others to learn. You will find your trainer takes a very personal approach, helping each individual to make the very most of their time in the classroom.

Further information
Contact Julia Brazier or Gill Loader
Esperan
Unit 1, Hilldrop Lane
Ramsbury
Wiltshire SN8 2RB
UK
Tel +44 (0)1672 520101
Fax +44 (0)1672 521039
Email info@esperan.com