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Course Description
 | Further Verification with Verilog |
Date: from 31 Aug 2000 to 1 Sep 2000
2 day(s)
English Ramsbury, Wiltshire UK
750,00 UK£ 30% for Europractice
Overview
As ASIC and large FPGA designs grow in complexity, verification is becoming the largest challenge in getting design projects completed on time. This specialized course is designed to give engineers with 3 - 18 months of Verilog based design experience an increase in productivity by teaching them advanced techniques in Verilog based testbench design and verification that can immediately be applied to existing and new design projects.
Course Agenda
Introduction to key verification concepts and terms
Overview of verification challenges
Verification in the design flow
Dynamic and static verification methods
Dynamic functional verification concepts
Advanced techniques for stimulus creation with Verilog
Random numbers and mathematical packages
File read operations
Script-driven testbenches
Opening and closing of files for flexible, efficient stimulus control
Coding specific types of test for complex designs
Stress and performance tests
Adaptive and directed testing
Random, sweep and boundary testing
Regression tests
Real world tests
Testbench building blocks and language specific coding tips for capturing the response from simulation and reporting on results
File write operations
Format conversion and ASCII visualisation of values
Hierarchical references for internal monitoring
Use of force and release
Vector capture and playback
Code constructs, testbench architectures and techniques for verifying simulation results
Overview of result comparison methods
Self-checking testbench architectures
Verification with self-checking designs
Regression testing with signature generation
Checking specific timing characteristics
Bus monitors, protocol checkers and interface design
Other verification tools and technologies
Test quality measurement
Coding techniques and software tips for improving simulation speed
Trade-offs in the use of types and assignments
Memory modeling issues
Static memory modeling
PLI based memory modeling
Conditional compilation
Simulation snapshots
Workshop Labs
The lab sessions will at least include
Using a random number generator to create a model which randomly inverts bits in a frame-based data stream, with a controlled probability, to mimic
transmission errors.
Prerequisites
Students should have between three and eighteen months of working experience using the Verilog language on at least one real-world design project.
Trainer Expertise
Esperan has over 40 regular trainers, who are themselves design consultants working on some of the world`s most advanced projects ranging from multi-million gate ASIC projects to those involving state of the art programmable logic devices. We have hand-picked each trainer for their up to date experience, combined with their presentation skills and flair for helping others to learn. You will find your trainer takes a very personal approach, helping each individual to make the most of their time in the classroom
Esperan
Unit 1 Hilldrop Lane
Ramsbury
Wiltshire
SN8 2RB
UK
Tel +44(0)1672 520101
Fax +44(0)1672 521039
Email info@esperan.com
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