Course Description

Duration 5 day(s)

Language English    Venue Killiney Court Hotel, Killiney, Co. Dublin, Ire

Country 

Course fee 1460,00    Currency EURO    Discount 1300 for groups of 2 or more

Description
This course covers key issues in front-end circuit design, PLLs and VCOs. It addresses modelling at both device and circuit level.
Layout and packaging issues are covered and illustrative practical examples are provided. Days 1 and 5 are presented by researchers from industry.
The course notes are supplemented by the textbook `Design of Radio-Frequency Integrated Circuits` by Thomas Lee,Cambridge University Press 1988.

Course Contents and Time Table
Day 1: Dr. Fred Weiss
· Brief review of RF fundamentals
· Design considerations for Low Noise Amplifiers
· Design considerations for active mixers

Day 2: Prof. Michiel Steyaert
· Towards the full integration of wireless front-end circuits in deep-submicron technologies
· Wireless CMOS front end circuits and systems

Day 3: Prof. Michiel Steyaert
· Basic PLL circuits. Prescalers
· Low phase noise VCO`s in CMOS
· Single chip CMOS synthesisers

Day 4: Prof. Georges Gielen
· Modelling for RF: device and circuit level
· RF analysis techniques
· Phase noise analysis of oscillators and synthesizers

Day 5: Mr. Steve Brett
· Technology, partitioning and architecture
· Layout and packaging issues
· Chip level simulation and verification
· RFIC examples

Audience
Who should attend?
This course is aimed at RFIC designers who already have some experience. There is strong emphasis
on industrial applications and the course concludes with a look at some relevant examples.

Further information
Registration can be done on-line at
www.itslimited.ie or by contacting ITS
directly.

Office Manager: Cathie Clare
Tel: + 353 1 272 0115
Fax: + 353 1 272 1076