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Course Description
 | Further Verification with VHDL |
Date: from 4 Oct 2000 to 5 Oct 2000
2 day(s)
English Ramsbury, Wiltshire UK
750,00 UK£ 30% for Europractice
Overview
As ASIC and large FPGA designs grow in complexity, verification is becoming the largest challenge in getting design projects completed on time. Following on from materials presented in our five day VHDL Application Workshop, this specialized course is designed to give experienced engineers an increase in productivity by teaching them advanced techniques in testbench design and verification that can immediately be applied to existing and new design projects.
Course Agenda
Introduction to key verification concepts and terms
Overview of verification challenges
Verification in the design flow
Dynamic and static verification methods
Dynamic functional verification concepts
Advanced techniques for stimulus creation with VHDL
Random numbers and mathematical packages
Advanced TextIO read applications in VHDL`87 and VHDL`93
Script-driven testbenches
Dynamic opening and closing of files for flexible, efficient stimulus control
Coding specific types of test for complex designs
Sweep tests
Adaptive tests
Boundary testing
Self-testing designs
Regression tests
Uses of random test data
Stress and performance tests
Directed tests
Real world tests
Testbench building blocks and language specific coding tips for capturing the response from simulation and reporting on results
Advanced TextIO write applications in VHDL`87 and VHDL`93
Extensions to basic TextIO
Data IO using binary format files
Constructing meaningful messages for assertion statements
Six methods of capturing the value of internal design objects
Typical issues in vector capture and playback
Code constructs, testbench architectures and techniques for verifying simulation results
Overview of result comparison methods
Self-checking testbench architectures
"On-line" and "off-line" result checking
Verification with self checking designs
Regression testing with signature generation
Checking specific timing characteristics
Bus monitors, protocol checkers and interface design
Other verification tools and technologies
Test quality measurement
Coding techniques and software tips for improving simulation speed
Trade-offs in the use of signals and variables
Memory modeling issues
Static memory mmodelling using data abstraction and shared variables
Dynamic memory modelling using access types
Linked lists, FIFOs and dynamic data structures
Conditional compilation
Simulation speed overhead of TextIO and foreign interfaces
Workshop Labs
The lab sessions include :-
File IO and visualization lab
Creating code to read and write standard file formats in ASCII and binary
Using a TCL-based file viewer to verify results
Error injector lab
Using a random number generator to create a model which randomly inverts bits in a frame-based data stream, with a controlled probability, to mimic transmission errors
Using the model to check a "hamming code" error corrector model and estimate the efficiency of the unit
Regression testing using signature generation
Writing a signature generation model to capture the inputs and outputs from a simple regression simulation
Using the model to verify a number of alternative architectures
Efficient memory modelling
Re-coding a functional description of a large memory model using a variety of static and dynamic modelling techniques to achieve a reduction in simulation time and resources.
Prerequisites
Students should have between three and eighteen months of working experience using VHDL on at least one real-world design project.
Trainer Expertise
Esperan has over 40 regular trainers, who are themselves design consultants working on some of the world`s most advanced projects ranging from multi-million gate ASIC projects to those involving state of the art programmable logic devices. We have hand-picked each trainer for their up to date experience, combined with their presentation skills and flair for helping others to learn. You will find your trainer takes a very personal approach, helping each individual to make the very most of their time in the classroom.
Esperan
Unit 1 Hilldrop Lane
Ramsbury
Wiltshire
SN8 2RB
UK
Tel +44(0)1672 520101
Fax +44(0)1672 521039
Email info@esperan.com
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