Course Description

Duration 2 day(s)

Language French    Venue Paris, France

Country 

Course fee 800,00    Currency UK£    Discount 30% Europractice member

Description
This two days workshop is designed for engineers who are new to using Altera APEX devices, and covers the Quartus software along with a detailed study of CPLD’s architecture, and design and implementation techniques.

Research by Altera has shown that engineers who have attended training in their technologies create designs that are 90% faster and 45% smaller, resulting in an average 70% parts cost saving!

This workshop is therefore a must for all engineers using Altera APEX technologies in their designs. Based upon Altera`s own training materials, the workshop presents the details of all technology features found in the APEX family of devices and how to use the Quartus place and route software to obtain the most efficient results.

Course Contents and Time Table
Introduction to Altera Devices and APEX
-20K Device Family Overview
-Introduction to Quartus Development
-System
-Design Entry methods
-Quartus Revision Control and Interface
-Timing Analysis
-Compile Design
-Reporting Timing Results
-Fmax, Setup, Hold, Clock to Out Analysis
-Paths Analysis
-Setting up Timing Requirements
-Multi-Clock Frequency Analysis
-Slack Analysis
- Multi-Cycle Assignments
-Floorplan Editor
-Floorplan Views
- Assignments from Floorplan Editor
-Viewing Delays
-Simulation
-Supported Simulation Methods
-Simulating with 3rd Party Simulators
-Simulator Settings
-Running Simulation
-Creating Vector Waveform File
-Setting Stimuli
-Result Analysis and Comparison
-Scripting
-Running a Script in Quartus
-Tcl/Tk Console
-Quartus API
-Tcl/Tk Basics
-Tcl/Tk Application examples

Day 2

-APEX 20 K Architecture and Features
-APEX 20K MegaLAB
-Dedicated Inputs, Clocks
-APEX 20K Logic Element
-Register Packing
-Carry and Cascade Chains
-Implementing Memory Functions
-Embedded System Block
-RAM/ROM in ESB
-Memory Configurations
-Implementing CAM
-EAB as CAM Features
-CAM Application Examples
-Implementing P-Term Functions
-ESB as Product-Term
-Comparison of LUT and Product-Term
-Parallel Expanders
-Implementing Product-Term Logic
-APEX 20K Interconnect
-MegaLAB Interconnect
-LAB Interconnect
-Lab-Wide Control Signals
-Row and Column Routing
-APEX 20K I/O Features
-Altera MultiVolt Circuitry
-Individual Node Features
-APEX 20K(E) I/O Element
-Row and Column I/O Pins
-Low-Voltage I/O Support
-LVDS
-ClockLock & ClockBoost with PLL
-ClockLock and ClockBoost Circuitry
-ClockLock Circuitry Advantage
-ClockLock Specifications
-APEX 20K ClockBoost Applications
-APEX 20KE PLL Features
-LVDS Interfacing
-Optimizing Designs for APEX 20K Devices
-Targeting Logic Elements
-ESBs Considerations
-APEX 20K(E) Interconnect
-APEX 20K(E) PLL
-Assignments and Optimizations
-Assigning Logic Options
-Timing Driven Compilation
-Assigning Cliques
-Location Assignments
-3rd Party Synthesis Tools
-APEX 20K In-System Considerations, Configuration
-Configuration Control
-Configuration Modes
-Configuration Data
-Steps of Configuration for PS and PPS
-The Quartus Interface
-Setting Device and Pin Options
-Creating a Chain Description File
-Setting Up JTAG Chain
-Programming Options
-In System Considerations
-Signal Tap
-Configurations and Resources
-The Quartus Interface
-Hardware Interface
Workshop Labs:

The Labs will get you familiar with the implementation/synthesis and timing analysis tools involved in the creation of a basic
APEX design using Quartus.

Audience
Students should be familiar with the issues and principle of digital hardware design, and how to operate the user interface within a PC based operating system. While some previous exposure to other FPGA/CPLD devices would be useful, it is not essential.

Further information
Gil Loader
Esperan
Tel +44 1672 520101
Fax +44 1672 521039
Email info@esperan.com

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