Course Description

Duration 2 day(s)

Language French    Venue Vélizy, France

Country 

Description
In this course, you will use the Virtuoso Analog Design Environment to model systems with Verilog-A components, called modules.
Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components.

You will learn how to use the Verilog-A syntax, the proper structure for Verilog-A modules, and how to generate symbols for your modules for use in a system hierarchy.
You will use Verilog-A to model and design an A/D converter (ADC) and a phase-locked loop (PLL).
The class also discusses using the Modelwriter and AHDL debug tools.
Formatting of output data, and the use of waveform filters to improve simulation performance are also discussed.

Learning Objectives:
* Provide information on the Verilog-A language and syntax.
* Empower the student to create and edit Verilog-A modules.
* Provide the student with adequate information to develop Verilog-A modules that model behavior and structure.
* Enable the student to verify that the Verilog-A modules properly describe the intended function.
* Allow the student to run simulations using Verilog-A modules.
* Introduce the student to software design tools that facilitate model development.

Course Contents and Time Table
# Modeling concepts: describing a system
# Structures of Verilog-A modules
# Designing in the Analog Design Environment
# Module interface declarations
# Ports, port directions, and parameters
# Natures and disciplines
# Signal flow and conservative models
# Defining behavior
# Time-dependent behavior
# Conditional behavior
# Mathematical operations
# Waveform filter functions
# Control of simulator functions
# Creating and simulating an A/D converter
# Creating and simulating a phase-locked loop
# Formatting data and file operations
# Development, Modelwriter, and AHDL Debug tools.
# Using LaPlace and Z-Transforms (optional)

Audience
* Analog IC Designers
* Design Engineers
* Analog Designers
* ASIC Designers
* Analog/Mixed-Signal IC Designers

Further information
Mr Antoine Chevalier
Position: Education Service Operational Mgr
Telephone: +33 134 88 53 48
Fax: +33 1 34 88 53 51
Email: antoine@cadence.com