Course Description

Duration 1 day(s)

Language English    Venue Feldkirchen-Munich, Germany

Country 

Description
In this course, you use Encounter® RTL Compiler global synthesis to debug problems in the synthesis of complex designs when optimizing for timing, area, and power. You also learn to use the synthesis flow to achieve better quality of results for the place-and-route tools.

Course Contents and Time Table
In this course, you:

- Analyze and fix the design constraints
- Analyze the results to debug and fix the timing of a design
- Identify best practices for synthesizing complex designs
- Apply retiming to fix the timing of a complex block
- Optimize the leakage and dynamic power of a design


Course Agenda

Day 1

- Analyze the results
- Retiming
- Optimizing Power
- Best practices

Audience
- ASIC Designers
- Logic Designers
- Digital IC Designers


Prerequisites

Before taking this course, you need to:

- Take the Encounter RTL Compiler basic course
- Have some experience using Encounter RTL Compiler
- Have a basic understanding of synthesis flows

Further information
Ms Gabriele Hasenberger
Ms Ileana Karagialani
Ms Marita Kuhn

training_germany@cadence.com