Course Description

Duration 2 day(s)

Language English    Venue Vélizy-Paris, France

Country 

Description
This is an Engineer Explorer class that is designed around more advanced topics and exploration of the tool.

This course does not teach basic tool operations. We require that students who are not actively using the tools first complete the Allegro® PCB Editor course, the Allegro® Package Designer course, or the Allegro® Design Entry HDL Front-to-Back Flow course.

The Allegro® High-Speed Constraint Management course uses a series of lectures, examples, and hands-on experience to deliver the information you need to apply and verify high-speed constraints across your design process.

This course will use examples to show you how to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, match the propagation delay of driver and receiver pairs, and more

Course Contents and Time Table
In this course you will learn to:

- Define specific net scheduling of high-speed nets.
- Match the propagation delay of nets and connections.
- Define minimum and maximum propagation delays for nets and connections.
- Identify high-speed constraint violations.
- Identify all the high-speed constraints that you can apply to the nets in your designs.
- Create Spacing and Physical constraints as well as area constraints and class to class rules
- Customize worksheets.
- Create formula based constraints
- Create customized constraints using SKILL


Software

The labs for this course require one of the following:

- Allegro PCB Design XL series product
- Allegro PCB Design L series product with the Performance Options
- Any IC Packaging product
- Any Allegro SI product

Audience
- This course is for PCB designers and package designers who need to constrain the high-speed nets in their designs.

Prerequisites

The student must be familiar with the Allegro PCB Editor, Allegro Package Designer, or Allegro Design Entry software.