Course Description

Duration 2 day(s)

Language English    Venue Bracknell, UK

Country 

Description
This unique, two day hands-on workshop is designed for engineers who are unfamiliar with low power design techniques and who need to design digital hardware systems that have minimum power consumption. The workshop is focused on engineers who require an in-depth background in low power principles and an overview of conventional low power design techniques being used by RTL ASIC designers.

In today’s ASIC design world, engineers need to be considering power consumption if they are either designing battery based products, or if their designs are sufficiently large that there are likely to be power dissipation problems for packaging. Designs which are larger than 500K gates and running at 200MHz or faster are the kinds of designs which are now needing a design methodology which takes power consumption into account.

Esperan has a proven track record in presenting courses which directly relate to real world, state of the art design issues. Following that philosophy, this workshop has a minimum of theory and focuses on the practical steps that engineers can take to reduce power consumption at every stage of the design process, from system design, through RTL coding down to gate level design issues. The final part of the course looks at four very different types of system applications, and recommends the approach to take in creating a low power based design in each case.

Course Contents and Time Table
The workshop covers the following areas:

* Forces driving low power design - application, packaging, reliability and technology drivers for low power
* Low power background – power dissipation mechanisms in CMOS digital circuits;
* Power analysis - how power can be measured at various points in the design process
* Key low power design techniques - Voltage and activity reduction and trade-offs;
* Architectural design - how decisions made at the system level can be used to reduce power consumption
* Arithmetic design - data representation and the implementation of arithmetic resources
* RTL design - the affect of architectural decisions made when coding designs at the register transfer level
* Synthesis and physical design - options for power management in synthesis, floorplanning and routing.
* Clock gating and activity analysis - application, measurement and analysis of clock gating
* Clock distribution issues - clock distribution techniques in a large ASIC device, and the affect on power consumption
* PLL and clock gating issues - Overview of PLL application to clock gating, switching and division

Further trends in low power design
Application examples - four very different types of system applications, and recommendations on the approach to take in creating a low power based design in each case

Lab Exercises
Rather than just presenting concepts, this workshop includes a real world design example where students have the chance to re-code parts of an RTL VHDL or Verilog based design in order to reduce the power consumption. Using simulation based RTL power analysis tools, students can get instant feedback on the affect of their coding styles on the power consumption of their designs.

Audience
ASIC design engineers who have little or no experience of low power design and who require a detailed insight into low power fundamentals and an overview of the design techniques and methodologies used for low power design.

Lecturers
Esperan has over 40 regular trainers, who are themselves design consultants working on some of the world`s most advanced projects ranging from multi-million gate ASIC projects to those involving state of the art programmable logic devices. We have hand-picked each trainer for their up to date experience, combined with their presentation skills and flair for helping others to learn. You will find your trainer takes a very personal approach, helping each individual to make the very most of their time in the classroom.

Further information
Please contact ESPERAN for the course fee.
Contact: Steve Tippins
Esperan LtD
Phone +44 1672 520101
Fax +44 1672 521039
Email info@esperan.com