Course Description

Duration 5 day(s)

Language English    Venue Slovak University of Technology

Country Slovakia

Course fee 250,00    Currency EURO    

Description
Power Aware physical design techniques, timing and power closure.

The 5-day Advanced Digital Physical Implementation flow will start by introducing the challenges for 90 nm SoC design and the design environment and too chain. The course will proceed with digital synthesis, leakage-aware design, design planning and floorplanning, library analysis and management.

The course will focus upon low power design flow covering techniques to minimise dynamic and static power consumption, multiple clock tree synthesis, test and multimode and multicorner optimisation. IR-drop analysis, dynamic power analysis sign-off and design finishing and layout verification will be covered. Extensive hands-on labs are part of the course.

Course Contents and Time Table
DAY 1

LECTURE 1: INTRO: WHAT ARE THE NEW CHALLENGES TO DESIGN 90NM SOCS
LECTURE 2: DESIGN ENVIRONMENT & TOOL CHAIN
M. WILMOTT - STFC
This session introduces 90nm digital IC design, giving an overview of the topics that are covered throughout the remainder of the course, including: Technology Changes, Design and Verification, Test Strategy, Low Power Techniques, Physical Implementation and Signoff Technologies. The morning concludes with an introduction to the 90nm EDA tools and implementation flows.

LECTURE 3 + LAB: DESIGN SYNTHESIS
M. WILMOTT - STFC
This session looks in detail at modern synthesis technologies: including topographical synthesis (with physical constraints), low power optimisation (both static and dynamic power), and Scan Test (with compressed scan).


DAY 2

LECTURE 4: LEAKAGE AWARE DESIGN / PREVENTION
G. VANWIJNSBERGHE - IMEC
Not only the fabs but also the chip architects and IC designers must contribute to the leakage reduction by combining techniques and materials on several fronts.

LECTURE 5 + LAB: DESIGN PLANNING AND FLOORPLANNING
G. VANWIJNSBERGHE - IMEC
Floorplanning & power network implementation and analysis including IR drop and electro migration analysis. Multi Voltage and Low Power requirements impact design hierarchy and power grid and necessitate the introduction of Voltage Islands, Isolation Cells, MTCMOS, ...

LAB 2: DESIGN PLANNING

LECTURE 6: LIBRARY ANALISYS AND MANAGEMENT (STANDARD CELL, IO, MEMORY)
LECTURE 7: IP INTEGRATION AND MANAGEMENT (HARD-, SOFT-, ANALOG IP)
G. VANWIJNSBERGHE - IMEC
To perform a good Place & Route, one has to know how to use the available libraries. This includes topics like operating conditions, min-max corners and multi Vth.


DAY 3

LECTURE 8 + LAB: LOW POWER FLOW, POSITIONING THE DIFFERENT TECHNIQUES TO MINIMISE DYNAMIC AND LEAKAGE POWER, CONSEQUENCE ON THE FLOW
G. VANWIJNSBERGHE - IMEC + W. KUZMICZ - WUT
Dynamic & leakage power minimization and how to use a unified power intent specification to assure coherence over the design flow and to allow verification of the power features. This includes always on buffer/register usage.

LECTURE 9: PHYSICAL SYNTHESIS - PLACEMENT AND OPTIMISATION
G. VANWIJNSBERGHE - IMEC
How do we move from a the synthesized gate level description and floorplan to a physical hierarchy and how do we deal with Hard Macro?s in such a Hierarchical and MultiVoltage design.

LECTURE 10: MULTIPLE CLOCK TREE SYNTHESIS
G. VANWIJNSBERGHE - IMEC
How does clock tree synthesis work at 90nm especially in the light of multi voltage designs, gated clocks and other low power techniques and the impact on skew and insertion delay.


DAY 4

LECTURE 11: PHYSICAL SYNTHESIS ? DESIGN FOR TEST (DFT)
G. VANWIJNSBERGHE - IMEC
DFT techniques & chain (re)stitching and its (usually) positive impact on the design

LECTURE 12: PHYSICAL SYNTHESIS ? MULTIMODE AND MULTICORNER
G. VANWIJNSBERGHE - IMEC
How to make sure that the chip is going to work in all the different operation modes (functional, BIST, Scan test, ...) and, when using MultiVoltage, in multiple corners.

LECTURE 13: PHYSICAL SYNTHESIS - ROUTING TO GDS2
G. VANWIJNSBERGHE - IMEC
How to route clock and signals nets and to optimize post route and perform crosstalk analysis and fixing.

LAB 4: PHYSICAL SYNTHESIS
G. VANWIJNSBERHGE - IMEC + W. KUZMICZ - WUT


DAY 5

LECTURE 14: IR DROP ANALYSIS, REQUIREMENT TO DO DYNAMIC POWER ANALYSIS IN 90NM
LECTURE 15: INTRODUCTION TO MULTIMODE MULTI-CORNER SIMULATION, ON-CHIP VARIATION AND STATISTICAL STATIC TIMING ANALYSIS
G. VANWIJNSBERHGE - IMEC

LAB 5: SIGNOFF ANALYSIS INCLUDING DYNAMIC GATE IR ANALYSIS AND STATIC TIMING ANALYSIS INCLUDING SIGNAL INTEGRITY
G. VANWIJNSBERHGE - IMEC + W. KUZMICZ - WUT

LECTURE 16: SIGN-OFF
G. VANWIJNSBERGHE - IMEC
Sign-off Extraction and all the analyses needed to be sure that the chip will work. What to do if there are violations. What can we do early in the flow to make sure not to get any surprises.

LECTURE 17: DESIGN FINISHING & LAYOUT VERIFICATION
G. VANWIJNSBERGHE - IMEC
Principles of pattern fill, parasitic extraction & layout verification (ERC, DRC, LVS)

LECTURE 18: TAPE-OUT
G. VANWIJNSBERGHE - IMEC
Tape-out issues, data preparation & documentation.

Audience
The course targets Professors, Post-docs and PhD students involved in the lectures and lab exercises in the European academia with engineering master curricula.

Lecturers
M. WILMOTT - STFC
G. VANWIJNSBERGHE - IMEC
W. KUZMICZ - WUT

Further information
idesa@rl.ac.uk