Top Eurotraining Course Directory
 
 

Course Description



Quality labelled course   

Circuit Challenges in Nanometer-Scale CMOS


Date: from 4 Jul 2005 to 8 Jul 2005

Duration 5 day(s)

Language English    Venue Lausanne, Switzerland

Country 

Course fee 1900,00    Currency EURO    Discount 15% for student or faculty

Description
These courses are aimed at providing engineers with up-to-date information on important current issues of design in analog and mixed-mode integrated circuits. This year, the subjects proposed are particularly focused on Low-Voltage, Low-Power, RF, Testing Data-Converters, Transitor-Level, Power Management and Low-Noise design problems and solutions. In general, the content of the lectures covers introduction, state-of-the-art in the specific field and practical case studies. The intent is to give to the participants a broad coverage of hints and design methods to be applicable in practice.

Course Contents and Time Table
------------------------------
MONDAY, July 4
------------------------------
8:30 - 12:00 am
Nanometer-Scale CMOS Devices
T. Skotnicki, STMicroelectronics

1:30 - 5:00 pm
Reliability Challenges - Coping with Uncertainties
N. Hakim, Intel
------------------------------
TUESDAY, July 5
------------------------------
8:30 - 12:00 am
Power-Aware Circuit Design Techniques
D. Sylvester, Univ. of Michigan

1:30 - 5:00 pm
Scaling Effects in Analog Design in Deep Sub-Micron CMOS
K. Bult, Broadcom
--------------------------------
WEDNESDAY, July 6
--------------------------------
8:30 - 12:00 am
Interconnections in Nanometer-Scale Technologies
E. Friedmann, Univ. of Rochester

1:30 - 5:00 pm
High-Performance and Low-Power Global Signaling Strategies
D. Sylvester, Univ. of Michigan & Y. Leblebici, EPFL
------------------------------
THURSDAY, July 7
------------------------------
8:30 - 12:00 am
System-Level Challenges and Floor-Planning Issues
Y. Leblebici, EPFL

1:30 - 5:00 pm
ESD and Latchup Protection for Sub-100nm Technologies
H. Gossner, Infineon Technologies
------------------------------
FRIDAY, July 8
------------------------------
8:30 - 10:00 am
Issues in Compact Modeling of Nanoscale MOS Transistors
C. Enz, CSEM

10:30 - 12:00 am
More Moore… and After
A. Ionescu, EPFL

Audience
The prerequisite of the course is a basic knowledge of semiconductor devices and circuits. All levels of expertise (beginners, medium and advanced engineers) can benefit of this training. Also, company managers and marketing engineers may find useful information in the trends of modern techniques and applications presented in these classes

Lecturers
Klaas Bult, Broadcom, The Netherlands
Christian Enz, CSEM, Switzerland
Eby Friedmann, University of Rochester, New-York
Harald Gossner, Infineon Technologies, Germany
Nagib Hakim, Intel, California
Mihai Adrian Ionescu, EPFL, Switzerland
Yusuf Leblebici, EPFL, Switzerland
Thomas Skotnicki, STMicroelectronics, France
Dennis Sylvester, University of Michigan, Michigan

Further information
Vlado Valence
EPFL-STI-IMM-LEG
Bat. ELB 339, Station 11
CH-1015 Lausanne
Tel: +41-21-695-2222
Fax: +41-21-695-2220
valence@mead.ch (technical)
education@mead.ch (administrative)

  EuroTraining Course Directory ©2008