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Course Description
 | Behavioral Modeling with Verilog-AMS |
Date: from 22 Feb 2006 to 24 Feb 2006
3 day(s)
English Bracknell, UK
This advanced Engineer Explorer course provides an in-depth approach to behavioral modeling of analog and mixed-signal design blocks and systems.
Students are required to have a working knowledge of the Virtuoso® AMS Designer Simulator or to complete the course prerequisite of taking the Virtuoso AMS Designer course.
In this three-day course, you will learn how to create parameterized Verilog-AMS models for analog/mixed-signal blocks, and verify the functionality and performance using the Virtuoso AMS Designer Simulator.
In this course you will:
* Learn the concepts of behavioral modeling and when to employ models to advantage.
* Create Verilog®, Verilog-A, and Verilog-AMS behavioral models to perform given functions.
* Verify the functionality and performance of the models you create using the Virtuoso AMS Designer simulator.
* Generate a library of common functions for smoothing discontinuous behavior.
* Explore modeling interdependencies through creation fo specification-related testbenches.
* Behavioral modeling and top-down design
* Refresher in behavioral Verilog
* Introduction to the Verilog-AMS language
* Continuity issues in modeling
* Modeling common analog effects: limiting, wave-shaping and impedances
* Handling analog interdependencies: saturation, diffusion capacitance and clocked behavior
* Verilog-AMS mixed-signal operation
* Verilog-AMS modeling examples
* Adding model complexities
* Adding error checking and reporting
* General modeling procedures
Special Notes
* This is an advanced course. You are expected to run the Virtuoso AMS Designer software without assistance to solve loosely defined problems.
* Labs will be exploratory rather than step-by-step.
* Library Developers
* CAD Engineers
* Analog/Mixed-Signal IC Designers
* Modeling Engineers
Prerequisites
* You must have completed the Virtuoso AMS Designer course before taking this class.
* Being familiar with the Verilog-A language would help you gain the maximum benefit from taking this advanced Engineer Explorer course.
Cadence staff is responsible for customer training, many instructors have advanced degrees in either education or engineering as well as practical knowledge of the software and curriculum development. Technical Service Engineers also teach classes and draw on their experience by helping designers in the field.
Mr Antoine Chevalier
Position: Education Service Operational Mgr
Telephone: +33 134 88 53 48
Fax: +33 1 34 88 53 51
Email: antoine@cadence.com
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