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Course Description
| Transistor-Level Analog IC Design |
Date: from 25 Sep 2000 to 29 Sep 2000 4 day(s)
English EPFL, Lausanne, Switzerland
2700,00 CHF
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MONDAY, SEPTEMBER 25
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8:30 -12:00 am
CMOS Op-Amps Overview
Klaas Bult, Broadcom
1:30 -3:00 pm
Single-Stage Amplifiers
Klaas Bult, Broadcom
3:30 -5:00 pm
Noise in MOS Transistors
Klaas Bult, Broadcom
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TUESDAY, SEPTEMBER 26
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8:30 -10:00 am
Distortion
Klaas Bult, Broadcom
10:30 -12:00 am
Basic Sub-Circuits
Klaas Bult, Broadcom
1:30 -5:00 pm
Matching of MOS Transistors
Maarten Vertregt, Philips
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WEDNESDAY, SEPTEMBER 27
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8:30 -10:00 am
Simple & Two-Stage Op-Amp Structures
Klaas Bult, Broadcom
10:30 -12:00 am
Gain-Boosting and Settling Behavior
Klaas Bult, Broadcom
1:30 -5:00 pm
Modeling and Simulation for Mixed-Signal IC Design
Daniel Foty, RStream Communications
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THURSDAY, SEPTEMBER 28
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8:30 -10:00 am
Class-AB Output Stages
Klaas Bult, Broadcom
10:30 -12:00 am
Examples of Trouble-Shooting
Klaas Bult, Broadcom
1:30 -3:00 pm
Zener/Avalanche Diode Reference Circuit Design
Paul Brokaw, Analog Devices
3:30 -5:00 pm
Bipolar Transistor Voltage Reference
Paul Brokaw, Analog Devices
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FRIDAY, SEPTEMBER 29
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8:30 -12:00 am
Feedback and Frequency Stabilization Techniques
Paul Brokaw, Analog Devices
1:30 -3:00 pm
Low-Noise and AGC Amplifiers
Bob Blauschild, Consultant
The prerequisite for the course is a basic knowledge of semiconductor devices and circuits.
Paul Brokaw, Analog Devices, USA
klaas Bult, Broadcom, The Netherlands
Daniel Foty, RStream Communications, USA
Maarten Vertregt, Philips, The Netherlands
Caroline Huber, education@mead.ch
Vlado Valence, valence@mead.ch
Tel: +41-21-695-2222
Fac: +41-21-695-2220
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